`timescale 1ns / 1ps

module fc_2_top(
    input  wire         clk,
    input  wire         rst_n_fc,
    input  wire         start,
    output wire [47:0]  fc_output_data_monitor,
    output wire         fc_output_wren_monitor,
    output wire         done_o
    );
    
    wire [1:0]  input_data_addr;
    wire [1023:0] input_data;

    wire [6:0]   weight_addr;
    wire [255:0] weight;

    wire [4:0]   bias_addr; 
    wire [7:0]   bias;

    wire          fc_output_wren;
    wire  [47:0]  fc_output_data;
    wire  [4:0]   fc_output_addr;

    wire [1023:0] mul_data1;
    wire [255:0] mul_data2;
    wire [1279:0] mul_result;

    

    fc_input_ram_2 u_fc_input_ram(
        .addra(input_data_addr),
        .clka(clk),
        .douta(input_data)
    );

    fc2_weight_ram u_fc_weight(
        .addra(weight_addr),
        .clka(clk),
        .douta(weight)
    );

    fc2_bias_ram u_fc_bias(
        .addra(bias_addr),
        .clka(clk),
        .douta(bias)
    );

    mult_array2 u_mult_array(
        .clk(clk),
        .rst_n(rst_n_fc),
        .data1(mul_data1),
        .data2(mul_data2),
        .result(mul_result)
    );

    assign fc_output_data_monitor = fc_output_data;
    assign fc_output_wren_monitor = fc_output_wren;

    fc_2 u_fc_2(
        .clk_i(clk),
        .rst_n_i(rst_n_fc),
        .start_i(start),
        .done_o(done_o),

        .input_data_addr_o(input_data_addr),
        .input_data_i(input_data),

        .weight_addr_o(weight_addr),
        .weight_i(weight),

        .bias_addr_o(bias_addr),
        .bias_i(bias),

        .fc_output_wren_o(fc_output_wren),
        .fc_output_data_o(fc_output_data),
        .fc_output_addr_o(fc_output_addr),  

        .mul_data1_o(mul_data1),
        .mul_data2_o(mul_data2),
        .mul_result_i(mul_result)
    );

endmodule